Design of High Speed Sine Wave Flash Adc for Uwb Applications
نویسنده
چکیده
Multigigahertz flash ADC is limited by sampling clock timing jitter. Since it is used in high frequency applications it is essential to remove jitter effects which will reduce the efficiency of ADC. This paper describes the effect of clock transition time on the spurious free dynamic range of a CMOS sample and hold circuit. To improve SFDR the effect of finite clock transition time of the signal and sinusoidal signal sampling clock are considered that is mainly based on signal dependent non linearity model. Where a square wave clock exhibits a shorter transition time but more jitter susceptibility, sinusoidal clocking provides a longer transition time but shorter jitter spectrum. To verify this concept a 6GS/s, 4b flash ADC is designed along with this interpolation technique is added in order to reduce the power consumption achieving effective number of bits of 3.93 bits with a SNR of 22.9dB. GENERAL TERMS: Flash ADC, ENOB, SNR, SFDR, Jitter
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